Typically, integrated circuits (IC) are provided with an ESD (Electro Static Discharge) protection circuitry. The ESD protection circuitry protects parts of the IC by clamping ESD-stressed terminals during an ESD event, and serves to divert the electrostatic discharge current away from protected parts of the IC, and thus to dissipate the stress energy without damage to the IC.
It is known to provide such ESD protection circuitry to integrated circuits provided with power gating capabilities. Such integrated circuits typically include one or more on-die semiconductor switches, from hereon referred to as the gating switches, which connect local power supply and/or ground of one or more circuit blocks, from hereon referred to as a gated domain, to the main or continuous power supply and/or ground respectively. The gating switch has a low impedance in a closed (connecting) state, and a high impedance in an open (disconnecting) state. The power supply to the power gated domain can be enabled or disabled by the state of the gating switch. Thus, the power supply to a gated domain can be turned off temporarily when not needed, e.g. to reduce the overall power consumption of the integrated circuit or to reduce the noise level. This temporary shutdown time is also referred to as “low power mode” or “inactive mode”. When the circuit blocks of the gated domain are required again, they are activated to an “active mode” and the switch is put in the closed state, enabling the connection to the power supply or ground.
As described in M.-D. Ker; C.-Y. Chang; Y.-S. Chang: “ESD protection design to overcome internal damages on interface circuits of CMOS IC with multiple separated power pins”, Proceedings 15th Annual IEEE International ASIC/SOC Conference, p. 234-238, 2002, in case an integrated circuit has different circuit blocks with different power supplies, ESD stress applied to a circuit block may cause damage to the interface with another circuit block.
S. Sofer, Y. Fefer, Y. Shapira, “Indirect ESD stressing mechanism in a VLSI circuits having multiple isolated power domains”, Proceedings of 32nd ISTFA 2006, p. 389-392, 2006 describes that ESD stress applied to a circuit block may actually cause damage to an area located inside another circuit block which is isolated from the block to which the ESD stress is applied. Accordingly, in case an integrated circuit with gating capabilities is subject to an ESD event, the ESD stress may penetrate to the not-protected, gated domain(s) and damage parts of the gated domain(s), such as the semiconductor components at the interface of the power gated domain.